##############################
## Format for commands
##############################

Format 0 (register and register):
       4      4      4      4            12           4
    +------+------+------+------+------------------+------+
    | 00uv | reg1 | reg2 |  op  |                  | reg3 |
    +------+------+------+------+------------------+------+
    
    u = nothing
    v = nothing

    a) registers
    MOV reg1, reg3          reg1 = reg3
    
    b) bit operations
    AND reg1, reg2, reg3    reg1 = reg2 & reg3
    OR  reg1, reg2, reg3    reg1 = reg2 | reg3
    XOR reg1, reg2, reg3    reg1 = reg2 ^ reg3
    NOT reg1, reg3          reg1 = ~reg3
    
    LSL reg1, reg2, reg3      reg1 = reg2 << reg3
    ASR reg1, reg2, reg3      reg1 = reg2 >>> reg3
    ROT reg1, reg2, reg3      reg1 = reg2 rot reg3
    
    c) integer arithmetic
    ADD reg1, reg2, reg3    reg1 = reg2 + reg3
    SUB reg1, reg2, reg3    reg1 = reg2 – reg3
    MUL reg1, reg2, reg3    reg1 = reg2 * reg3
    DIV reg1, reg2, reg3    reg1 = reg2 / reg3
    

Format 1 (register and constant):
       4      4      4      4                16
    +------+------+------+------+-------------------------+
    | 01uv | reg1 | reg2 |  op  |            im           |
    +------+------+------+------+-------------------------+
   
    u = nothing
    v = extend with (0/1)

    a) registers
    MOV reg1, im            reg1 = im
    
    b) bit operations
    AND reg1, reg2, im      reg1 = reg2 & im
    OR  reg1, reg2, im      reg1 = reg2 | im
    XOR reg1, reg2, im      reg1 = reg2 ^ im
    
    LSL reg1, reg2, im      reg1 = reg2 << im
    ASR reg1, reg2, im      reg1 = reg2 >>> im
    ROT reg1, reg2, im      reg1 = reg2 rot im
    
    c) integer arithmetic
    ADD reg1, reg2, im      reg1 = reg2 + im
    SUB reg1, reg2, im      reg1 = reg2 – im
    MUL reg1, reg2, im      reg1 = reg2 * im
    DIV reg1, reg2, im      reg1 = reg2 / im
   
   
Format 2 (memrory):
       4      4      4                   20
    +------+------+------+--------------------------------+
    | 10uv | reg1 | reg2 |             offset             |
    +------+------+------+--------------------------------+
    
    LD reg1, reg2, offset   reg1 = Mem[reg2 + offset]
    ST reg1, reg2, offset   Mem[reg2 + offset] = reg1
    
    uv=00   (load word)
    uv=01   (load byte)
    uv=10   (store word)
    uv=11   (store byte)
   
Format 3 (branches):
    
    v=0 (just jump)
    v=1 (save ret address R15 = PC + 1)
    
    JMP arg                always
    JMI arg                if N
    JEQ arg                if Z
    JCS arg                if C
    JVS arg                if V
    JPL arg                if ~N
    JNE arg                if ~Z
    JCC arg                if ~C
    JVC arg                if ~V

       4      4                    20                 4
    +------+------+--------------------------------+------+
    | 110v | cond |                                | reg3 |
    +------+------+--------------------------------+------+
    
    arg = reg3
    PC = reg3
    
       4      4                      24
    +------+------+---------------------------------------+
    | 111v | cond |                offset                 |
    +------+------+---------------------------------------+
    
    arg = offset
    PC = PC + 1 + offset

#############################################
## Bytes for ops (f0/f1) and conditions (f3)
#############################################

MOV    0
AND    1
OR     2
XOR    3
NOT    4
ADD    5
SUB    6
MUL    7
DIV    8

LSL    9
ASR   10
ROR   11



V=0 - jump
V=1 - branch

MP/RC  0
MI     1
EQ     2
CS     3
VS     4
PL     5
NE     6
CC     7
VC     8
GE     9
LT    10

##############################
## Archtecture specification
##############################

32-bit RISC Architecture
16 registers (12 general porpouse)
    
Max memory specification:
    RAM: 127 kB (incl. peripherals)
    ROM: 2 MB   (use via offset)
         512 MB (use via reg)

Register map

    +--------+-------------------+-------------------------------------------------------+
    |   r#   |      porpouse     |                            note                       |
    +--------+-------------------+-------------------------------------------------------+
    | r0     | reserved for 0    | just an agreement, not strictly hardware like in MIPS |
    | r1-r12 | general porpouse  |                                                       |
    | r13    | stack pointer     | just an agreement                                     |
    | r14    | static base       | just an agreement                                     |
    | r15    | register for link | used by hardware (f3 with v flag)                     |
    +--------+-------------------+-------------------------------------------------------+


Specific device:
ROM: 4 kB
RAM: 512 B

Addresses
+- 0x000
|
|  ROM
|
+- 0x400
|
|  RAM
|
+- 0x470
|
|  Peripherals
|   0x470 - output part of gpio
|   0x474 - input part of gpio
|   0x478 - pwm settings
|   0x47C - seconds from start
|
+- 0x480

GPIO (0x470)
     1        1        1           1         1         1
 +--------+--------+-------     --------+---------+---------+
 | p0_out | p1_out | p2_out ... p29_out | p30_out | p31_out |
 +--------+--------+-------     --------+---------+---------+

GPIO (0x474)
     1       1       1          1        1        1
 +-------+-------+------     -------+--------+--------+
 | p0_in | p1_in | p2_in ... p29_in | p30_in | p31_in |
 +-------+-------+------     -------+--------+--------+

PWM (0x478)
     5       1      10       5       1      10
 +-------+------+--------+-------+------+--------+
 | pin_1 | en_1 | duty_1 | pin_2 | en_2 | duty_2 |
 +-------+------+--------+-------+------+--------+

##############################
## Test program
##############################

 0    mov r13 0x400       // r13 = 0x400 (SB)
 4    add r1 r0  12       // r1 = r1 + 12 = 12
 8    add r2 r1  -7       // r2 = r1 + (-7) = 5
12    and r3 r1  r2       // r3 = r1 & r2 = 4
16    jeq 20              // don't jump (Z=0)
20    sw  r3 r13 0x1      // mem[SB + 0x4] = r3 = 4
24    lw  r4 r13 0x1      // r4 = mem[SB + 0x4] = 4
28    sub r5 r4  10       // r5 = r4 - 10 = -6
32    sw  r5 r13 0x3      // mem[SB + 0x12] = r5 = -6
36    sw  r1 r13 0x70     // mem[SB + 0x70] = r1 = 12
40    jmp -4

********************************
01001110000000000000010000000000
01000001000001010000000000001100
01010010000101011111111111111001
00000011000100010000000000000010
11100010000000000000000000010100
10100011111000000000000000000100
10000100111000000000000000000100
01000101010001100000000000001010
10100101111000000000000000001100
10100001111000000000000001110000
11100000111111111111111111111100
